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A2065 Functional Specification
This information have been taken from the "A2065 System Schematics".Description
The A2065 Ethernet LAN Card controller implements the 802.3 type protocol which calls for 10 Megabits/sec CSMA/CD interface. It supports both 10Base2 Type B (Cheapernet) and 10 Base 5 Type A (thick Ethernet) connections. The design has been developed around the AMD LANCE chipset which is comprised of the Am7990 Local Area Network Controller for Ethernet, the Am7992B Serial Interface Adapter, the Am7996 IEEE-802.3 Ethernet/Cheapernet Transceiver, and other associated logic necessary to implement a complete Ethernet interface.
Architecture
A shared memory host interface was chosen because of the bus bandwidth requirements of the Am7990. A total of 32K of onboard buffering provided to act as a shared interface between the Am7990 and the Amiga CPU. This allows for worst case conditions of back to back Ethernet packets received by the board during loaded 68000 or graphics chip activity. In addition to the 32K of memory mapped packet memory, the Am7990's I/O registers are also mapped into the Amiga memory space as two sixteen bit locations. Finally, a small 256+4 Bit Prom is used to store the autoconfig data as well as the board's Ethernet address. The output side consists of both thick and thin (Cheapernet) Eternet interfaces. The thick interface comes directly from the Am7992B SIA with transformer isolation. To implement the Cheapernet section, various passive components along with an Am7996 are required.
Functionally, the Ethernet interface may be partitioned into the following sections: Transceiver interface, autoconfig and configuration logic, Bus control buffers and logic, and onboard control logic/buffering including the packet memory. In the following sections each subsystem will be explored and discussed in more detail.
Transceiver Interface
The A2065 supports two types of cable media. The fist is commonly called "Thick Ethernet" or 10Base5. Thick Ethernet is used mainly in large installations where many nodes must be supported and distances between active repeaters are long. Typically, a transceiver box is physically connected to the Thick Ethernet backbone and a drop cable provides the actul connection to the LAN interface card present in the computer. The Thick Ethernet connection is actually a 15 pin Female D connector on the A2065 board. This physical interface is driven directly via transformer isolation by the Am7992B SIA. The transformers provide DC isolation and are designed to meet IEEE specifications. The function of the Am7992B is to decode/encode Manchester type serial data strams as per IEEE specifications for Ethernet. The key circuitry surrounding the Am7992B is the 20 MHz crystal (X1), which must meet exacting specifications, and the5600pF VCO Phaselock look filter capacitor (C34). AMD data sheets call for a 5000 pF capacitor, but information from AMD applications engineers indicates that a value up to 6800 pF should be acceptable. Currently, this part is specified at 5600 pF ± 10% or better. Specifications for the 20 MHz crystal are set forth in the data sheet for the Am7992B. The jumper JP7 is supposed to affect the output signal for 802.3 applications. This jumper requires further testing and may need to be deleted for production. Thick Ethernet requires a +12, 0.750A supply. This is supplied directly from the Amiga Expansion connector. Note that a fuse is provided to protect against shors circuits which might damage the Amiga or associated peripherals.
The second type of media is Cheapernet, commonly referred to as "Thin Ethernet" or 10Base2. Cheapernet evolved as a result of media costs associated with Thick Ethernet. Cheapernet allows for a "Bus" topology with up to 100 nodes. Inexpensive RG58 coax is used along with BNC T connectors and terminators. The Cheapernet section is comprised of the AM7996, a +5V to 9V DCDC converter, and various passive components which differentially drive the coax media and also act to recover the incoming data stram. The Cheapernet section also implements collision detection for collisions occurring on the media. Refer to the AM7996 data sheets for a complete technical discussion of the operation of the Cheapernet transceiver.
Autoconfig logic and configuration logic
Autoconfiguration is accomplished by reading the 256*4 AutoID Prom and relocating the physical bas address of the Ethernet board within some 64K of Amiga I/O memory space. The autoconfig logic is implemented in the 16L8A PAL along with the Prom, the 74F521 address comparator, and the 74LS373 address latch. When the Ethernet board is ready for autoconfiguration, its _CONFIGIN line is brought low, address 0xE80000 is decoded, and a board select is generated. During the configuration process, the Prom parameters are read into memory to create the board's physical Ethernet address. The signal _IDP is generated from the 16L8A PAL to decode the Prom chip select. The read signal _RD to Prom is generated from the 20L8A PAL. Refer to the PAL equations for details. Once the Prom has been read, the Amiga will write to address 0xE800048 to load the onboard address latch. The Ethernet board will generate a write pulse called SATL to load a 74LS373 with the board's new base address. The SATL signal comes from the 16L8A PAL. It is generated from a decode of 0xE80000 and a write strobe called _SWR. The _SWR strobe comes from the 20R6A PAL. It is essentially a delayed write pulse using delayed AS and the 7M Amiga clock. Once the latch is written, _CONFIGOUT is generate, enabling the output buffer of the 74LS373 latch. The board is now relocated and will respond to its new address.
Bus Control bffers and control logic
The Ethernet board data path consists of a 16 bit (D15:D0) wide data bus and is used for reading and writing the Ethernet local memory and th Am7990 registers. Only 4 bits (D15:D12) are significant with respect to the AutoID Prom. Referring to Figure 1, a pair of 74LS245 and 74LS244 isolate the Amiga's system bus from the internal Data/Address paths. Only the Amiga 68000 or the Am7990 can have access to this interna data/address path at one time. Normally, tha Am7990 is burst DMA reading or writing the 32K memory as packets are being received or transmitted. The host 68000 requests access to this internal bus to either read/write memory or Am7990 registers. The 68000 acesses are arbitrated based on the Am7990 requiring the bus. A wait stated is inserted to guaranty meeting 60nx _AS to XRDY delay during arbitration time. The bus control function is implemented bu the 20R6A PAL. This PAL generates the data bus transceiver control _DBE. Thes signal is active when there is no exceptional conditions and a signal _ABE is active. _ABE is active only when the Am7990 is not requesting the internal bus (_HOLD, _LANCE not asserted). This satisfies the condition that mutually exclusive relationship exists between the 68000 and the Am7990. The Ethernet board also listens on _BERR for bus faults; if _BERR is ever active, _DBE will not be active. The signal _LANCE is generated to enable the LS244 buffers which pass the Am7990 DMA address thru to the Ram buffers. _LANCE in conjunction with _ABE determines which source (68000 or Am7990) drives the internal address path. The Am7990 works in a multiplexed address/data method. First an address is latched during the first part of the read/write cycle, then the actual data transfer occurs.
Onboard control logic/buffering
The onboard control logic consists mainly of chip selects and read and write strobes to memory and the Am7990. The 32K buffer is partitioned into a high banck and a low bank of 8K * 16 bits each. Address line A14 determines which bank is active. The read and write strobes to the memory are qualified by bus control signals. During 68000 R/W cycles, the signals READ, _UDS, and _LDS are used for the system bus along with _BSEL to control reading data. These same signals plus one generated onboard called _ENDCYC are used to generate write pulses. _ENDCYC is generated by the 20R6A PAL. During Am7990 bus ownership, a differen set of signals controls the R/W timing pulses. All these control signals are generated within the 20L8A Internal Bus control PAL. The 20L8A PAL also generates chip selects for the 32K memory and Am7990 I/O register. For further information, refer to the PAL euqtions and the Am7990 data sheed.
Low Level Interface Programming
For a complete discussion of programming the Ethernet board, refer to the Am7990 application sheets and the Ethernet device driver source. A brief explanation is given here. The Amiga configures the board and builds a config structure in memory. The Ethernet software goes out and finds the location of the board and reads the serial number. The serial number plus the manufaturer base Ethernet address make up the complete Ethernet address. The software then sets up the initialization block in the 32K memory which sets up two circular linked list buffers, one transmit and one receive queue. The initialization block refers to these queues as "descriptors". The Am7990 is then programmed via I/O transfers into internal registers for various network operational parameters, along with the setting up of an interrupu handler. Finally, the action starts. The network layeer software fills buffers to transmit, while emptying buffers that are filled from incoming packets.More to come...
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